Process Hierarchy

  Application Specific Integrated MEMS Exchange (ASIM-X)
Process characteristics:
Die size
The minimum chip size (width, length)is necessary to ensure robust photolithography.
Die size*
The minimum chip size (width, length)is necessary to ensure robust photolithography., must be 2.4 .. 5 mm
2.4 .. 5 mm
Device layer material silicon
Device layer thickness 40 .. 60 µm
Die count
Number of fabricated dies per chip site
  • This process flow and design rules were developed through the DARPA ASIMPS (“Application-Specific Integrated MEMS Process Service”) project and the DARPA ASIM-X project at Carnegie Mellon University. The ASIM-X micromachining occurs after the CMOS is completed and is summarized with the series of cross sections in Figure 1. The structures are made from the silicon substrate, including the back-end-of-line CMOS metaldielectric stack located on top of the substrate. The backside silicon deep reactive-ion etch step is setup to provide a silicon plate with a 50 µm ± 10 µm thickness on the frontside of the chip. The microstrutcures are then patterned from the frontside with a separate silicon DRIE step.
  • The metal layers in the CMOS process act as the etch mask for the frontside structural dielectric
    etch. The first metal layer to be encountered by the dielectric etch will mask the etch. The structural height is primarily determined by the silicon plate thickness. However, the appropriate metal and dielectric stack height must be added to the silicon height to determine the total height. Therefore, a discrete set of structure heights are available by specifying a particular metal etch-stop layer for the dielectric etch. For example, for a 4-metal CMOS process, four different structural heights may be specified. Gate polysilicon and any other CMOS layers that are placed under metal (including active device layers) are incorporated into the structure.
  • For the initial beta prototype run, the CMOS process will be restricted to one of the following
    • Jazz Semiconductor 4-metal 0.35 µm SiGe60 BiCMOS;
    die thickness is approximately 280 µm
    • TSMC 4-metal 0.35 µm CMOS
  • The beta users are responsible for purchasing the CMOS dice, most likely on a foundry multiproject run. Prior to tape-out, the submitted designs must pass the foundry design rules and the MEMS-specific design rules in this document.
  • Please see the design rules for ASIM-X in the document attached below.
[Thumbnail]asimx.png (77.8 KB, image/png)
attached by ozgur (Mehmet Ozgur) on 2006-07-18 12:13
Process description
ASIM-X DesignRules Apr5_06 v2.pdf (175.1 KB, application/pdf)
attached by ozgur (Mehmet Ozgur) on 2006-07-18 11:55