Process Hierarchy

  Silicon-On-Glass MEMS (SOG-MEMS)
Bonding Method
Wafer bonding method to be used
Anodic bonding (Si to Pyrex)
Design area
Active design area per chip site in a multi-user project runs
15 mm x 15 mm
Device layer material silicon
Device layer resistivity 1 .. 20 Ω*cm
Device layer thickness 100 µm
Die count
Number of fabricated dies per chip site
Substrate material Pyrex (Corning 7740)
  • The silicon on glass (SOG) module has been developed to integrate CMOS and high-aspect ratio MEMS sensors and actuators. This is accomplished by forming recesses on a glass wafer, anodically bonding a silicon wafer to that glass wafer, and using deep reactive ion etching to etch MEMS devices through the backside of the silicon wafer over the glass recess.
  • This process is primarily for capacitive sensors and actuators because the MEMS structures are fabricated by deep reactive ion etching (DRIE) of the bulk silicon. The movement of the structures is in the plane of the wafer. Therefore, electrode pads that connect CMOS and the MEMS externally are fabricated using bulk (low doping) silicon which has high resistance. This must be considered before choosing this process for your CMOS applications
  • Deadlines for the next run:
    Process Will Begin at Michigan: January 31, 2006
    Chips Returned to Customers: March 31, 2006
SOG_design_rules_v2_03-19-07.pdf (799.2 KB, application/pdf)
attached by ozgur (Mehmet Ozgur) on 2007-04-23 14:14
Revised design rules
[Thumbnail]sog_lr.jpg (165.7 KB, image/jpeg)
attached by ozgur (Mehmet Ozgur) on 2005-09-28 18:00
SOG-MEMS process flow
[Thumbnail]sog3.png (591.0 KB, image/png)
attached by ozgur (Mehmet Ozgur) on 2005-09-28 18:00
3D view of a SOF-MEMS device
[Thumbnail]sog2.png (61.5 KB, image/png)
attached by ozgur (Mehmet Ozgur) on 2005-09-28 18:00
SEM image of SOG-MEMS devices
[Thumbnail]sog1.png (79.3 KB, image/png)
attached by ozgur (Mehmet Ozgur) on 2005-09-28 18:00
Description of SOG-MEMS device